Interruption Handling

Timer/Counters
The AT89C51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. The AT89C52 has these two Timer/Counters, and in addition Timer 2. All three can be configured to operate either as Timers or event Counters. As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a Counter, the register is incremented in response to a 1 to- 0 transition at its corresponding external input pin, T0, T1, or (in the AT89C52) T2. The external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since 2 machine cycles (24 oscillator periods) are required to recognize a l-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. In addition to the Timer or Counter functions, Timer 0 and Timer 1 have four operating modes: (13 bit timer, 16 bit timer, 8 bit auto-reload, split timer). Timer 2 in the AT89C52 has three modes of operation: Capture, Auto-Reload, and baud rate generator.

Timer 0 and Timer 1

Timer/Counters 1 and 0 are present in both the AT89C51 and AT89C52. The Timer or Counter function is selected by control bits C/T in the Special Function Register TMOD (Figure 6). These two Timer/Counters have four operating modes, which are selected by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timer/Counters, but Mode 3 is different. The four modes are described in the following sections.

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